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Scope 14 1.1 Application 14 1.2 Inclusions 14 1.3 Exclusions 14 1.4 Definitions 15 Logical Specifications 16 Bus Pin Assignments 16 2.2 Signal Descriptions 17 Timing Specifications 24 Signal Time Sequences 24 Signal Time Durations 26 Electrical Specifications 28 CMOS Electrical Specifications 28 TTL Electrical Specifications 29 4.3 Terminations 30 Mechanical Specifications 32 Card Dimensions 32 Card Profile Dimensions 32 Bus Connector 32 Card Ejector 32 Card Keying 32 Bus Implementation 15 Bus Connector Pin Assignment 16 Address Selection Signal Sequence 5 Read Signal Sequences 25 Write Signal Sequence 26 Critical Read Timing 26 Critical Write Timing 27 Key Slot Placement and Dimensions for Card Polarity Keying 33 Bus Card Outline 34 Bus Edge Card Finger Design 35 Bus Card Outline-Metric 36 Bus Edge Card Finger Design-Metric 37 Power Bus Pin Assignments 17 Examples of Peripheral Timing Control Lines 20 Maximum Voltage Ratings for CMOS 28 Power Bus Voltage Ratings for CMOS 29 CMOS Logic Signal Voltage Ratings 29 Maximum Voltage Ratings for TTL 30 Power Bus Voltage Ratings for I"rL 30 TTL Logic Signal Voltage Ratings 30 Card Dimensions 32 Card Profile Dimensions for Minimum Spacing 3
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