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A Low-power Design Method Using Multiple Supply Voltages by Mutsunori Igarashi; Masahiro Kanazawa; Shinji Sonoda; Makoto Ichida; Naoyuki Hatanaka; Kimiyoshi Usami; Kazutaka Nogami; Fumihiro Minami; Yukio Kawasaki; Takahiro Aoki; Midori Takano; Chiharo Mizuno; Takashi Ishikawa is a scholarly article available to read on EtoBox.

What is A Low-power Design Method Using Multiple Supply Voltages about?

We present a low-power design method that utilizes the multiple supply voltages. The proposed method reduces the power consumption of random logic circuits by 47% on the average, with up to 15% area overhead, by the combination of "clustered Voltage Scaling (CVS) scheme" and "Bow by Row optimized Power &pply (RRPS) scheme". By the CVS scheme, the optimal netlist, that uses the minimized number of the level converters and the maximized number of the low Vdd gates under the timing constraints, is generated. To avoid the wiring resource consumption and the increase of the interconnect delay caused by the layout constraints of the multiple-supply-voltage design, a new power bus wiring scheme called "RRPS scheme" is proposed. The proposed method is applied to a media processor chip MpactTh' and achieved the above mentioned results. In this paper, the emphasis is put on the interrelation between the generation of the two-supply-voltage netlist with the CVS scheme and the layout technology, such as the power supply scheme and the placement of the multiple-supplyvoltage gates. The clocking scheme for the multiple supply voltages is also discussed.

Author

Mutsunori Igarashi; Masahiro Kanazawa; Shinji Sonoda; Makoto Ichida; Naoyuki Hatanaka; Kimiyoshi Usami; Kazutaka Nogami; Fumihiro Minami; Yukio Kawasaki; Takahiro Aoki; Midori Takano; Chiharo Mizuno; Takashi Ishikawa

Publisher

ACM Press

Published

1997

Language

EN