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Prediction of delay time for future LSI using on-chip transmission line interconnects by Takumi Uezono; Junpei Inoue; Takanori Kyogoku; Kenichi Okada; Kazuya Masu is a scholarly article available to read on EtoBox.

What is Prediction of delay time for future LSI using on-chip transmission line interconnects about?

An on-chip transmission-line interconnect has been proposed to reduce the delay time and power consumption. Transmission lines are used to replace long RC interconnects, and can greatly improve circuit performance. In this work, we estimate the performance of circuits using on-chip transmission line technologies, focusing on delay improvement. A derivation algorithm for the wire length of each path in a circuit is proposed. In simulated results, replacement with an on-chip transmission line can improve the critical-path delay by 10%.

Author

Takumi Uezono; Junpei Inoue; Takanori Kyogoku; Kenichi Okada; Kazuya Masu

Publisher

ACM

Published

2005

Language

EN