About this document

UART2BUS Verification Plan Overview by Sujay M is a document available to read on EtoBox.

This document provides a verification plan for the UART2BUS Open Core project. It describes the design specifications, system behavior, verification levels and tools, methodology, test scenarios, and coverage requirements. The design has ports for a clock, reset, internal address and data buses, and serial data in and out. It supports two modes of operation - a text mode using hexadecimal commands, and a binary mode with configurable byte commands. The verification plan outlines the methodology, test scenar

Author

Sujay M

Language

EN