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Acknowledgment -We gratefully acknowledge the collaboration of Prathima xi Agrawal in the development of CONTEST. We also acknowledge the help of Prof. S. C. Seth with the material in Chapter 2. We are thankful to Prof. Ernest Kuh of University of California at Berkeley for his support of the research reported in this book. When this work was done, one of the authors was a Ph.D. candidate at Berkeley and derived financial support from the NSF grant ECS-85-06901 and the State of California Microelectronics and Computer Research Opportunities Program. The collaboration between the two authors was made possible by a consulting support from the AT&T Bell Laboratories. ## X1i Chapter 1 ### 1.2. THE TESTING TECHNIQUES Large scale integration has added enormous complexity to the process of testing. This complexity is due mainly to the reduction in the ratio of externally accessible points (primary inputs and outputs) to internal inaccessible points in the circuit. We can classify the integrated circuit testing techniques into three broad Chapter 1 DFT SCANS PISie Ele LOGIC DESIGN PHYSICAL DESIGN WAFER FAB. Fig. 1.1 Conventional methodology of VLSI chip realization with automatic test gene

Author
Kwang-Ting (Tim) Cheng, Vishwani D. Agrawal
Publisher
Springer US
Published
1989
Language
EN
ISBN
9780792390251
Subjects
Engineering, Stem

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