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Parallelization of WHILE loops on pipelined architectures by Parthasarathy P. Tirumalai; Meng Lee; Michael S. Schlansker is a Computer Science article available to read on EtoBox.

What is Parallelization of WHILE loops on pipelined architectures about?

Modulo scheduling theory can be applied successfully to overlap Fortran DO loops on pipelined computers issuing multiple operations per cycle both with and without special loop architectural support. This paper shows that a broader class of loops--REPEAT-UNTIL, WHILE, and loops with more than one exit, in which the trip count is not known beforehand--can also be overlapped efficiently on multiple-issue pipelined machines. The approach is described with respect to a specific machine model, but it can be extended to other models. Special features in the architecture, as well as compiler representations for accelerating these loop constructs, are discussed. Performance results are presented for a few select examples.

Who reads Parallelization of WHILE loops on pipelined architectures?

Author

Parthasarathy P. Tirumalai; Meng Lee; Michael S. Schlansker

Publisher

Springer US; Springer-Verlag; Kluwer Academic Publishers; Springer Science and Business Media LLC; Publons; Society for Mining, Metallurgy and Exploration Inc. (ISSN 0920-8542)

Published

1991

Language

EN

Field

Computer Science (Physical Sciences)