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About this Engineering article
Repeater stage timing analysis for VLSI resistive interconnects by Chandel, Rajeevan; Sarkar, S.; Agarwal, R.P. is a Engineering article available to read on EtoBox.
It is typically read by researchers, students, and practitioners in Engineering.
- Author
- Chandel, Rajeevan; Sarkar, S.; Agarwal, R.P.
- Publisher
- Emerald Group Publishing Limited; Emerald (MCB UP ); Emerald Group Publishing Ltd.; Emerald (ISSN 1356-5362)
- Published
- 2006
- Field
- Engineering (Physical Sciences)
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