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A Floating-Point Unit Architecture Based On SweRV EH1 Core by divyamallikarjun2020 is a document available to read on EtoBox.

This paper presents the design and implementation of a tightly-coupled Floating-Point Unit (FPU) based on the RISC-V SweRV EH1 core, which supports the RV32F instruction set. The FPU achieved a performance improvement of 4.5 times over the original core, with a Whetstone benchmark score of 1.13 MWIPS/MHz, and was verified through simulation and FPGA prototyping using TSMC 90nm process technology. The design includes various functional units for floating-point operations and was successfully validated with b

Author

divyamallikarjun2020

Language

EN