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What is Enhanced CPU Design for SDN Efficiency about?

This paper presents an enhanced CPU design for Software-Defined Networking (SDN) controllers using a ternary system to improve network management. The proposed Multiple-Valued Logic (MVL) circuit demonstrates significant improvements in chip area, propagation delay, and energy consumption compared to traditional binary circuits. The study introduces a new 1-trit Ternary Full Adder (TFA) that reduces propagation delays by over 99% compared to existing designs, optimizing CPU utilization in SDN environments.

Author

Darren Chin

Language

EN