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This paper discusses a low-jitter charge-pump phase-locked loop (PLL) designed in 90-nm CMOS technology for SerDes transmitter clocking, capable of supporting data rates from 1 to 10 Gb/s. It features a programmable dual-path loop filter for flexible bandwidth and peaking adjustment, and an LC-VCO with a 45% calibration tuning range to minimize jitter and improve performance. The PLL is integrated into SerDes transceiver macros, addressing design considerations for noise reduction and manufacturability in d

Author

hspark

Language

EN