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The document discusses delay in VLSI circuits. It defines propagation delay and contamination delay, which describe how long it takes for an output to change after an input changes. It discusses how to optimize timing at different levels, from architecture to layout. It then describes RC delay models which approximate transistor behavior with resistances and capacitances to estimate delay. Common gates like NAND and NOR are characterized by their logical effort and parasitic delay. The linear delay model ex

Author

Haseeb Chughtai

Language

EN