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What is FPGA Optimized Decimal Floating Point Adder about?

This document describes the FPGA implementation of a decimal floating point adder that complies with the IEEE 754-2008 standard. It uses an equal bypass adder to reduce power consumption and delay by reducing gate count. The design supports the decimal64 format and can be extended to decimal128. It was implemented on a Virtex-5 FPGA and tested successfully with several test vectors.

Author

IOSRjournal

Language

EN