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Sradha M is an electrical and electronics engineering graduate with a CGPA of 9.23. She has skills in hardware modeling, RTL design, computer architecture, and tools like Verilog and Vivado. For her undergraduate thesis, she implemented a level set algorithm on a Zedboard FPGA and designed an FPGA-based line follower bot. Currently she is a pre-doctoral fellow at IISC working on a 5G/MMW antenna transceiver. Past experiences include internships at Toboids Automata designing PCBs and at TCS Rapid Labs develo

Author

skrxbbr7nh

Language

EN