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9-T SRAM Cell for Reliable Ultralow-Power Applications and Solving Multibit Soft-Error Issue by Soumitra Pal; Aminul Islam is a Engineering article available to read on EtoBox.

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Higher noise tolerance, lower power consumption and higher reliability are the major design metrics for designing an SRAM cell. It is difficult to achieve an SRAM cell with stable operation at low-voltage for low power consumption due to increasing variations in process, voltage and temperature (PVT). It is proved that conventional 6T fails to maintain its stability in scaled technology especially in deep-subthreshold regime. Furthermore, it does not support column bit-interleaving architecture. Therefore, it is very much prone to multi-bit softerror. In this paper a double-ended read-decoupled ultralowpower 9T SRAM cell (LP9T) is proposed and the proposed cell supports the column bit-interleaving architecture. Because of read-decoupled technique its noise tolerance is improved. To show the effectiveness of the proposed cell, it is compared with other recently published SRAM cells, namely fully differential 8T (FD8T), single-ended read-disturb-free 9T (SEDF9T) and Ultra-Dynamic Voltage Scalable 10T (UDVS10T). The proposed cell provides 1.2×/2.3× higher read current (I READ ) compared to UDVS10T/SEDF9T. Furthermore, LP9T shows 3.8×/11.6× improvement in read delay compared to FD8T/UD

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Author

Soumitra Pal; Aminul Islam

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Published

2016

Language

EN

Field

Engineering (Physical Sciences)