About this document
Chip Planning in VLSI Design by lmcet Principal is a document available to read on EtoBox.
Chapter 3 of the document focuses on chip planning in VLSI physical design, covering topics such as floorplanning, optimization goals, and various representations of floorplans. It discusses algorithms for floorplan sizing, pin assignment, and power routing, emphasizing the importance of minimizing area and wirelength. The chapter also introduces terminology related to floorplans, including constraint graphs and sequence pairs.
- Author
- lmcet Principal
- Language
- EN