About this Engineering article
Test Pattern Generation and Clock Disabling for Simultaneous Test Time and Power Reduction by Jih-Jeen Chen; Chia-Kai Yang; Kuen-Jong Lee is a Engineering article available to read on EtoBox.
It is typically read by researchers, students, and practitioners in Engineering.
- Author
- Jih-Jeen Chen; Chia-Kai Yang; Kuen-Jong Lee
- Publisher
- IEEE; Institute of Electrical and Electronics Engineers; Institute of Electrical and Electronics Engineers (IEEE) (ISSN 0278-0070)
- Published
- 2003
- Language
- EN
- Field
- Engineering (Physical Sciences)