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This paper introduces a Ternary Ripple Carry Adder (TRCA) design that utilizes a Ternary 3:1 multiplexer and Ternary Half and Full Adders, aiming for reduced power consumption and latency. The proposed circuit outperforms existing designs in terms of latency and power-delay product, making it suitable for high-performance ternary computational applications. The study highlights the advantages of ternary logic over binary logic, particularly in reducing chip area and improving energy efficiency in digital ci

Author

rowdyh20

Language

EN