About this document
A 12 Bit 8 47 FJ Conversion Step Capacitor Swapping SAR ADC in 110 by 朱弘妃 is a document available to read on EtoBox.
This paper presents a 12-bit successive approximation register (SAR) ADC that utilizes a capacitor-swapping technique to enhance linearity while maintaining low power consumption. The ADC, fabricated in a 110-nm CMOS process, achieves a figure-of-merit of 8.47 fJ/conversion-step and operates at a conversion rate of 1 MS/s with measured DNL and INL within 0.3 LSB and 0.56 LSB, respectively. The proposed design effectively addresses capacitor mismatch issues without requiring larger capacitor sizes, thus opti
- Author
- 朱弘妃
- Language
- EN