About this document
Logical Effort in Circuit Design by Carlos Saavedra is a document available to read on EtoBox.
The document discusses how extra bootstrap capacitance between the input and output of an inverter has a greater effect on delay than extra capacitance between the input and ground. It provides an example circuit with two inverter pairs, one with an extra 3 fF capacitor between the input and output of the second inverter, and the other between the input and ground. The pair with capacitance between input and output sees a slower transition on its output node a due to the extra charge that must be supplied t
- Author
- Carlos Saavedra
- Language
- EN