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Weighted Pseudorandom TPG Design by Srujana Reddy N.V. is a document available to read on EtoBox.
What is Weighted Pseudorandom TPG Design about?
The document presents a weighted pseudorandom test pattern generator (TPG) designed for built-in self-test (BIST) architectures, aimed at enhancing chip testing efficiency as submicron technology evolves. It discusses the limitations of conventional testing methods and proposes a new approach that utilizes Galois Fields to improve randomness and fault coverage while optimizing area and delay. The proposed TPG has been implemented using Verilog and VIVADO, demonstrating promising results in reducing power co
- Author
- Srujana Reddy N.V.
- Language
- EN