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A coarse-grained FPGA architecture for high-performance FIR filtering by James R. Anderson; Siddharth Sheth; Kaushik Roy is a scholarly article available to read on EtoBox.

What is A coarse-grained FPGA architecture for high-performance FIR filtering about?

This paper introduces a coarse-grained FPGA architecture that is specialized for highperformance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar to that of a custom ASIC design, while allowing all of the basic FIR design, parameters, including coefficient precision, to be configured. Previous research has already shown that FPGAs can provide a high-performance alternative to DSP processors. Experimental comparisons in this paper show that the performance and area efficiency of the proposed architecture is similar to that of custom approaches across a wide range of filter sixes and configurations.

Author

James R. Anderson; Siddharth Sheth; Kaushik Roy

Publisher

ACM Press

Published

1998

Language

EN