About this document
Full Subtractor Dataflow Verilog Code by rajeevrvs083 is a document available to read on EtoBox.
This document describes a full subtractor module in Verilog. It defines the module with inputs A, B, C and outputs Diff and Borrow. It assigns Diff to be the XOR of A, B, and C and assigns Borrow to be the OR of AND expressions involving A, B, and C. It also includes a testbench module that initializes and tests the full subtractor module with different input combinations over time.
- Author
- rajeevrvs083
- Language
- EN