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Digital timing macromodelling for VLSI design verification by Jeong-Taek Kong, Kong, David V. Overhauser is a book available to read on EtoBox.

What is Digital timing macromodelling for VLSI design verification about?

<p><P><b>Digital Timing Macromodeling for VLSI Design Verification</b> first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. <br> The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addresse

Author

Jeong-Taek Kong, Kong, David V. Overhauser

Publisher

Springer-Verlag New York, LLC

Published

2012

Language

EN

ISBN

9781461523215

Subjects

Engineering, Computer Science, Stem