Can I read Prefetcher-based DRAM Architecture on EtoBox?

Prefetcher-based DRAM Architecture by Jaiswal, Saurabh; Gupta, Shailendra Kumar; Dandapat, Soumya Soubhagya is a scholarly article available to read on EtoBox.

What is Prefetcher-based DRAM Architecture about?

Advancement in Processor technology has made it easy to handle data-intensive workloads, but limiting main memory advances has created performance bottlenecks. In DRAM, there have been improvements in DRAM access latency as well as reduction in cost-per-bit with the increase in cell density. But still DRAM data transfer rate lags behind the processing speed of the current generation processors. As Memory advancements based on hardware have been progressing at a slower pace, to cope up with High-end Processors, Architectural level advancements such as Prediction techniques, Replacement policies, etc are the major subject. In the recent field of research, Data prediction is a sought out topic as correct prediction can boost performance by decreasing the amount of excess memory access by predicting data beforehand using data access trends and behaviors. Though prediction techniques have been implemented at most of the Computer Architecture, We propose implementing data prediction in DRAM level architectures like TL-DRAM and CROW. Both of these method distributes the DRAM into different parts which contain a smaller section which is faster and larger section which contains the bulk of

Author

Jaiswal, Saurabh; Gupta, Shailendra Kumar; Dandapat, Soumya Soubhagya

Published

2021

Language

EN