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Routing Congestion in VLSI Circuits: Estimation and Optimization (Series on Integrated Circuits and Systems) by Prashant Saxena; Rupesh S Shelar; Sachin S Sapatnekar is a nonfiction available to read on EtoBox.

What is Routing Congestion in VLSI Circuits: Estimation and Optimization (Series on Integrated Circuits and Systems) about?

With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling. There is an inherent tradeo? between choosing a minimum delay path for interconnect nets, and the need to detour the routes to avoid “tra?c jams”; congestion management involves intelligent allocation of the available int- connect resources, up-front planning of the wire routes for even distributions, and transformations that make the physical synthesis ?ow congestion-aware. The book explores this tradeo? that lies at the heart of all congestion m- agement, in seeking to address the key question: how does one optimize the traditional design goals such as the delay or the area of a

Who reads Routing Congestion in VLSI Circuits: Estimation and Optimization (Series on Integrated Circuits and Systems)?

Author

Prashant Saxena; Rupesh S Shelar; Sachin S Sapatnekar

Publisher

Springer Science+Business Media, LLC

Published

2007

Language

EN

ISBN

9780387300375

Category

nonfiction

Subjects

Computer Science, Management, Engineering