About this document
Dual-DLL Clock-Deskewing Circuit Design by Quốc Doanh is a document available to read on EtoBox.
This document presents a clock-deskewing circuit (CDC) using a master-slave delay-locked loop (MSDLL) configuration to synchronize clocks for core-to-core links without dummy elements for phase compensation. The dual-locking CDC effectively compensates for mismatches in interconnected wires, I/Os, and clock buffers, utilizing a folded coarse-fine voltage-controlled delay line (FCF-VCDL) for wide-range operations. Implemented in 0.18-µm CMOS technology, the CDC operates from 20 MHz to 2 GHz with a power diss
- Author
- Quốc Doanh
- Language
- EN