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What is CMOS D-Latch Design in 180nm Tech about?

This paper discusses the design and characterization of CMOS D-latch circuits in 180nm technology using Cadence Virtuoso and Spectre simulator. Key findings include a clock-to-Q delay of 0.1142 ns, power consumption of 16.84 µW, and a 45% power savings compared to SR latch implementations. The study also highlights the effects of capacitive loading and identifies clock overlap failure modes.

Author

Aditya Raj

Language

EN