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Built-in Harmonic Prediction Scheme for Embedded Segmented-Data-Converters by Kim, Byoungho; Abraham, Jacob A. is a Engineering article available to read on EtoBox.

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Increase in manufacturing test cost is of paramount issue to chip suppliers, which has been primarily due to costly external testers and long test-time. This paper proposes a loopback-based self-test technique to cost-effectively predict the dynamic nonlinearities of on-chip segmented digital-to-analogconverter (DAC) and analog-to-digital-converter (ADC), by externally looping a DAC back to an ADC, through an external load board employing two parallel paths: a programmable-gain-amplifier (PGA) path and a bypass path for test purpose. A segmented DAC (or ADC) consists of coarse and fine DACs (or ADCs). Two loopback tests are sequentially performed. For the first loopback test, a clean and single-tone sinusoidal signal is applied to a coarse DAC, and it bypasses a fine DAC for test purpose. The obtained DAC output is then fed to a coarse ADC through a bypass path on the load board. Simultaneously, the DAC output is applied to a fine ADC through a PGA path, so that the DAC output signal can fit into the input full-scale range of the fine ADC. For the second loopback test, a sinusoid is fed to a fine DAC, and it bypasses a coarse DAC in this time. Similarly, the DAC output is then appl

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Author

Kim, Byoungho; Abraham, Jacob A.

Publisher

Institute of Electrical and Electronics Engineers; Institute of Electrical and Electronics Engineers Inc.; Institute of Electrical and Electronics Engineers (IEEE); Research Square (ISSN 2169-3536)

Published

2020

Language

EN

Field

Engineering (Physical Sciences)