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A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC by Smith, Jennifer Pearl (author);Bailey, J. I. (author);Tuthill, John (author);Stefanazzi, Leandro (author);Cancelo, Gustavo (author);Treptow, Ken (author);Mazin, Benjamin A. (author) is a Engineering article available to read on EtoBox.

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Many digital signal processing applications require a channelizer capable of moving sections of the incoming spectrum to baseband quickly and efficiently with minimal spectral leakage and signal distortion. We report the design and implementation of a 4 GHz, 4096-branch, 8-tap, 2/1 oversampled polyphase channelizer implemented on a Xilinx RFSoC. The open-source design consists of only IP cores created using Vivado HLS (C++) and IP cores available in Vivado HLx and System Generator versions 2019.1+. The channelizer was tested using a PYNQ overlay and Jupyter Notebook (Python) hosted on the RFSoC embedded CPU. The design uses 24% of the LUTs, 9% of the DSP48s, and 11% of the BRAMs on the ZCU111 RFSoC evaluation board and meets timing constraints at 512 MHz. The oversampled polyphase channelizer suppresses spectral image components below -60 dB. This design provides the first example of an oversampled polyphase channelizer running on a system on a chip architecture created without direct use of hardware description language. The presented approach leverages high-level design tools and includes source code which can be readily adapted by other researchers and development teams without

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Author

Smith, Jennifer Pearl (author);Bailey, J. I. (author);Tuthill, John (author);Stefanazzi, Leandro (author);Cancelo, Gustavo (author);Treptow, Ken (author);Mazin, Benjamin A. (author)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Published

2021

Language

EN

Field

Engineering (Physical Sciences)