About this document
Enhancing VLSI Wireload Models by vincentvln is a document available to read on EtoBox.
The document discusses wireload models which synthesis tools use to estimate wire characteristics like delay in the absence of physical layout data. It explores common myths and misconceptions around wireload models, including that the model should always be based on total block area, that one model per area is sufficient, that wire resistance and area can be ignored, and that vendor models can always be trusted. The document advocates testing assumptions and describes measuring model quality to potentially
- Author
- vincentvln
- Language
- EN