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High-Speed Ring Amplifiers for SAR ADCs by shane10435139 is a document available to read on EtoBox.
What is High-Speed Ring Amplifiers for SAR ADCs about?
This thesis reviews ring amplifier topologies and proposes a split input stage design to enhance speed properties without stacking transistors. A pipeline-assisted SAR ADC utilizing a ring amplifier is implemented, achieving an SNR of 58 dB and SFDR of 71 dB at 550 MHz with a power consumption of 3.3 mW. The findings indicate that while ring amplifiers are suitable for high-speed applications, they are limited by lower settling speeds.
- Author
- shane10435139
- Language
- EN