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Sub-Threshold Digital CMOS Logic Analysis by phanindra21 is a document available to read on EtoBox.
12 The document discusses operating digital logic gates in the sub-threshold region to achieve ultra-low power consumption. It analyzes CMOS and Pseudo-NMOS logic operating in the sub-threshold region and compares the results to CMOS operating in the normal strong inversion region and energy recovery logic. Simulation results show an exponential reduction in power consumption of two orders of magnitude for an 8x8 carry-save array multiplier operated in the sub-threshold region. 10 Delay 8 6 4 2 0 0.
- Author
- phanindra21
- Language
- EN