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What is Akhter 2019 about?

This paper introduces a modified binary multiplier circuit based on Vedic mathematics, which enhances efficiency in terms of delay and area compared to previous designs. The proposed circuit is implemented in VHDL and simulated for various bit sizes, demonstrating significant performance improvements. The results indicate that the modified Vedic multiplier can be extended for larger bit sizes and offers reduced delay and LUT requirements.

Author

rao.dwh92

Language

EN