About this scholarly article

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC - A 3.3 V-only 16 Mb flash memory with row-decoding scheme by Atsumi, S.; Umezawa, A.; Kuriyama, M.; Banba, H.; Ohtsuka, N.; Tomita, N.; Iyama, Y.; Miyaba, T.; Sudoh, R.; Kamiya, E.; Tanimoto, M.; Hiura, Y.; Araki, Y.; Sakagami, E.; Arai, N.; Mori, S. is a scholarly article available to read on EtoBox.

Author

Atsumi, S.; Umezawa, A.; Kuriyama, M.; Banba, H.; Ohtsuka, N.; Tomita, N.; Iyama, Y.; Miyaba, T.; Sudoh, R.; Kamiya, E.; Tanimoto, M.; Hiura, Y.; Araki, Y.; Sakagami, E.; Arai, N.; Mori, S.

Publisher

IEEE

Published

1996

Language

EN