About this document

4-Bit Register VHDL Code Example by Rodrigo Crt is a document available to read on EtoBox.

This document describes a 4-bit register entity with an input port P, a clock input CLK, a load input LOAD, and an output port Q. The architecture uses a process sensitive to the clock CLK, input P, and load signal LOAD. When the clock CLK transitions to 1 and the load signal LOAD is 1, the input P is assigned to the output Q, loading the input value into the register.

Author

Rodrigo Crt

Language

EN