About this document
VLSI Project: 64-bit Full Adder Design by ak622774 is a document available to read on EtoBox.
This project report details the implementation of a 64-bit full adder using Simvision and the design of an 8-transistor (8T) 1-bit full adder layout using Cadence Virtuoso. The objectives include verifying the functionality of the full adders through simulation and layout analysis, ensuring performance and power efficiency. The findings contribute to advancements in digital design methodologies and provide insights for future digital circuit implementations.
- Author
- ak622774
- Language
- EN