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VLSI generalised digit serial architecture for multiplication, division and square root by A.E Bashagha is a Computer Science article available to read on EtoBox.

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A novel digit serial combined arithmetic unit for multiplication, division and square root which can be pipelined to the bit level is presented for the "rst time. The proposed module is based on radix-2L arithmetic. As a result, it is general for any digit size, n, and can be derived in a straightforward manner without the need to bit parallel or bit serial designs as an initial starting point. Moreover, any adder can be used in the controlled add/shift/subtract basic cell of the generalised digit serial unit. Two digital basic cells are proposed; the "rst cell is based on the conventional carry feedback adder and hence, the digit serial structure can be pipelined to the digit level only. The second digital cell is based on the carry fed forward adder. The feed forward of the carry out bit allows subdigit pipelining to increase the computation speed. This will give designers greater #exibility in "nding the best trade-o! between hardware cost and throughput rate. An evaluation of the proposed structure is also presented. It is shown that the bit level pipelined digit serial architecture can achieve better performance than the conventional carry feedback digit serial design and the

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Author

A.E Bashagha

Publisher

Elsevier Science; Elsevier ; Elsevier BV (ISSN 0165-1684)

Published

1999

Language

EN

Field

Computer Science (Physical Sciences)