About this document
Logical Effort in Skewed Inverters by anil rajput is a document available to read on EtoBox.
This document appears to be homework instructions from a professor for EECS 141 at the University of California. It includes 3 problems related to digital circuit design. Problem 1 involves calculating logical effort for skewed inverters and designing clock distribution networks. Problem 2 involves sizing gates in an OR logic circuit to minimize propagation delay for different load capacitances. Problem 3 involves sizing inverters in a clock distribution network and calculating the energy drawn and dissipat
- Author
- anil rajput
- Language
- EN