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This document discusses the design of low power square-law CMOS composite cells for use in analog multiplier circuits operating at low voltages. It describes existing single transistor and conventional composite transistor square-law cells and their limitations for low voltage operation. It then presents a new low voltage composite cell design and a low power square-law composite cell design that aims to reduce power consumption while maintaining square-law behavior for use in low voltage analog circuits. S
- Author
- anishdatla
- Language
- EN