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Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07 - Using standard asic back-end for qdi asynchronous circuits by Najibi, Mehrdad; Saleh, Kamran; Pedram, Hossein is a scholarly article available to read on EtoBox.

What is Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07 - Using standard asic back-end for qdi asynchronous circuits about?

Asynchronous circuits already have shown their benefits. The main drawback is the lack of powerful CAD and layout generation tools limiting the widespread use of the asynchronous methodology. QDI asynchronous circuits are known as a powerful category of asynchronous circuits targeting performance and power driven design. In this paper we addressed standard cell implementation of the template based QDI circuits utilizing standard layout generation tools. This is achieved by analyzing and removing outer cell isochronic fork constraint which is the main timing constraints limiting the standard layout generation. The isochronic fork free final netlist has 10-20% area overhead in average which is the cost of facilitating the use of standard CAD tools.

Author

Najibi, Mehrdad; Saleh, Kamran; Pedram, Hossein

Publisher

ACM Press

Published

2007

Language

EN