About this document
Minimizing Clock Skew in Pipelines by ybbvvprasada rao is a document available to read on EtoBox.
This paper presents a new method to minimize clock skew in multiple pipeline systems by using uniform clock distribution through parallel ports. A single clock pulse normally creates skew between pipeline stages due to different clock path lengths. The new method uses parallel ports on a microcontroller to simultaneously supply clock pulses to individual pipelines. This avoids skew by ensuring clock pulses reach each pipeline at the same time. The hardware configuration and microcontroller algorithms for im
- Author
- ybbvvprasada rao
- Language
- EN