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Design and Analysis of PVT Invariant Current Reference in 65-nm CMOS by Nishant Maurya; Nijwm Wary is a scholarly article available to read on EtoBox.

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In this paper, a CMOS current reference circuit has been proposed for achieving a PVT compensated current. The design is based on a modified version of the beta multiplier circuit with an on-chip resistor implemented using transistor in the deep triode region. Compensation of process corner variation is done by using a process tracking circuit (PTC). Temperature variation compensation is achieved by cancelling the PTAT variation of the beta multiplier circuit with the CTAT gate voltage of the on-chip transistor based resistor. The design has been implemented in 65 nm CMOS technology and simulated in Cadence specter. The current reference achieves a process variation of 1.4% and it has a temperature coefficient of 276.8 ppm/ oC over a temperature range of 0oC to 100oC. The reference current generated in this design is 8.8 μA with a supply voltage of 1.2 V, giving a net power consumption 126.56 μW.

Author

Nishant Maurya; Nijwm Wary

Publisher

IEEE

Published

2022

Language

EN