About this scholarly article

2016 20th International Symposium on VLSI Design and Test (VDAT) - On minimization of test power through modified scan flip-flop by Ahlawat, Satyadev; Tudu, Jaynarayan T. is a scholarly article available to read on EtoBox.

Author

Ahlawat, Satyadev; Tudu, Jaynarayan T.

Publisher

IEEE

Published

2016

Language

EN