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This paper discusses the design of low-power successive approximation register (SAR) analog-to-digital converters (ADCs) for small radar receiver applications, highlighting improvements in energy efficiency from 3 pJ/conversion-step in 2000 to 0.4 fJ/conversion-step in 2019. It provides an overview of the operational principles, error analysis, and state-of-the-art design techniques for various components of SAR ADCs, emphasizing their suitability for applications requiring high energy efficiency. The paper

Author

Mohammad Zakaria 064

Language

EN