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This document presents a reinforcement learning approach to optimize parallel prefix circuits like adders. An RL agent is trained to design prefix circuits using a grid-based state-action representation and environment. The trained agents produce prefix adder circuits that achieve up to 16.0% lower area for the same delay compared to existing baselines in 32-bit settings, and up to 30.2% lower area in 64-bit settings. The agents are trained using open-source synthesis tools and cell libraries, and can achie

Author

cs Tian

Language

EN