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Fail-Safe Microprocessor Interlocking System by Nikunj Aggarwal is a document available to read on EtoBox.

What is Fail-Safe Microprocessor Interlocking System about?

This paper presents a fail-safe microprocessor-based railway interlocking system installed at Pukou station near Nanjing, China. The system includes a Basic Interlocking System (BIS) and a Safety Assurance System (SAS) that use diverse redundancy to ensure fail-safety. Fault tree analysis shows the system will enter a safe state, keeping switches stable and signals red, if any of 30 critical faults occur, avoiding catastrophic failures. It provides improved safety, reliability, and maintainability over prev

Author
Nikunj Aggarwal
Language
EN

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