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FPGA-Based Digital Signal Processor Design by Chinavenkateswararao G is a document available to read on EtoBox.

This document describes a thesis submitted by Arifa Parveen to the National Institute of Technology in Rourkela, India. The thesis proposes designing and implementing a 32-bit digital signal processor (DSP) using Verilog HDL and field programmable gate array (FPGA) technology. The DSP is demonstrated by performing convolution on two input sequences using three instruction formats: register, immediate, and jump. The design and simulation of individual modules like the multiplier-accumulator, control unit, ar

Author

Chinavenkateswararao G

Language

EN