About this document
IC Design Project Report by sagar.sahu.mtech.2025 is a document available to read on EtoBox.
This document details a mini project focused on designing a CMOS inverter library and buffer chain to analyze power, performance, and area trade-offs in digital integrated circuits. It covers objectives such as creating a standard-cell style inverter library, understanding layout design, and implementing Verilog models for delay and power analysis. The project emphasizes the impact of technology scaling on performance and power consumption, providing insights for future VLSI design studies.
- Author
- sagar.sahu.mtech.2025
- Language
- EN