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Novel Asynchronous Adders by H. Boddapati; A. Naregalkar; B. L. Raju is a scholarly article available to read on EtoBox.

What is Novel Asynchronous Adders about?

Digital battery operated mobiles and implanted devices require maximum battery life. Extended battery life can be achieved by either operating at the lowest possible supply voltage or operating at the slowest possible speed. The advantages of Asynchronous circuits make it suitable for low power operation of the circuits. Asynchronous circuits stops computing when there is no change in the input there by eliminating the need for extra complexity of clock gating. The reduction in power also minimizes the efforts for the heat dissipation and cooling expenses. Low power and low energy techniques such as minimizing the number of transistors, voltage scaling are used. The implication of voltage scaling is a wide range of variation in the delay. Adders are representative of signal processing architectures. Asynchronous Adder circuits dissipate less power in applications where performance is nonlimiting. Asynchronous adders can be implemented using static or dynamic circuits. Asynchronous dynamic adder circuits employ a single rail or dual rail logic or a combined logic. In this work Three Novel low power Asynchronous Full Adder circuits are proposed. The Circuits are implemented using cad

Author

H. Boddapati; A. Naregalkar; B. L. Raju

Publisher

ACM Press

Published

2011

Language

EN