About this document
Power Optimization Techniques in VLSI by himaece is a document available to read on EtoBox.
This document summarizes power optimization techniques for VLSI layout. It discusses four main sources of power dissipation in CMOS circuits: leakage current, short-circuit current, standby current, and capacitive current. The document reviews techniques to reduce power at various levels of design including reducing chip capacitance through scaling, lowering supply voltage, employing better design techniques, and using power management strategies. It focuses on physical design automation techniques for powe
- Author
- himaece
- Language
- EN